培訓(xùn)方式以講課和實(shí)驗(yàn)穿插進(jìn)行。
Cadence? Incisive? Enterprise Simulato主要利用系統(tǒng)級(jí)至門級(jí)的涵蓋率來驅(qū)動(dòng)功能驗(yàn)證和除錯(cuò)分析進(jìn)一步促進(jìn)的驗(yàn)證的效率及可預(yù)測性。Cadence Incisive Enterprise Simulator?提供testbench制作、共用和分析能力，可從系統(tǒng)級(jí)至RTL再到門級(jí)驗(yàn)證其設(shè)計(jì)，利用此環(huán)境從計(jì)劃至完成皆可支援涵蓋范圍驅(qū)動(dòng)的運(yùn)算法，而其原位編譯的模組可在傳統(tǒng)同步模擬加速並同時(shí)模擬關(guān)于behavior、transation(TLM)?、RTL和門級(jí)模型，以達(dá)到有效改善同步模擬的不良性能。它也支援工業(yè)標(biāo)準(zhǔn)的驗(yàn)證語言並且與開放驗(yàn)證運(yùn)算法相容(OVM)，因此工程師能迅速簡單地整合Cadence Incisive Enterprise Simulator以建立所需要的驗(yàn)證流程。
COURSE OUTLINE
MDV (Metric Driven Verification) foundations workshop
·?????????MDV Foundations introduction
–??MDV Foundations Planning
–??Introduction to Planning
·?????????Verification Plan Development
–??Lab 1: Launching Your First Regression
–??Lab 2: Review the Default vPlan View in Enterprise Manager
–??Lab 3: Creating Reusable Verification Plans
–??Lab 4: Creating a Top Level Verification Plan
–??Lab 5: Detecting Changes in the New Specification
–??Lab 6: Review the vPlan in vManager
·?????????MDV Foundations Infrastructure ?
–??Lab 1: Your First Enterprise Manager Regression
–??Lab 2: Integrating project build and run
·?????????MDV Foundations Management
–??Lab 1: Create your own first failures view
–??Lab 2: Rerun Failures
–??Lab 3: vPlan Analysis
–??Lab 4 : Report generation
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Low Power Verification Workshop
???????????Introduction
–????????Introduction to Low Power Terminology
–????????CPF Creation
–????????Lab: Understanding the power information from a CPF file - Solution
???????????Low Power Simulation Verification
–????????Verification Planning and Metrics for Low Power
–????????Low-Power Simulation
–????????TCL Commands for Debug
–????????Debugging with SimVision
–????????Automatic Assertions
–????????Lab: Low-Power Simulation Debug
Assura Verification
The Assura? Verification course covers aspects of using the Assura DRC and Assura LVS tools for design rule checks, short location, and layout-versus-schematic checks. In labs, the student executes DRC and LVS and debugs error results.
Learning Objectives
In this course you will:
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o Verify your physical IC design with Assura Verification?
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o Set up and run DRC and LVS?
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o?Locate and display results from DRC and LVS runs?
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o Run verification in various input and run modes
Audience
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o CAD Developers
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o Design Engineers
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o? Layout Designers
Prerequisites
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o Layout design experience
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o Physical verification experience
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o UNIX OS
Course Agenda
Unit 1
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o?Introduction?
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o?Using Assura Verification?
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o?Operational details?
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o?Inputs and outputs?
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o?Interactive debugging environment?
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o?DRC and LVS runs
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o?Running design-rule checks (DRC)?
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o?DRC error debugging techniques?
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o?Error Layer Window?
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o?Setting up DRC run parameters
Unit 2
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o?Running design rule checks (continued)?
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o?Antenna check?
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o?Density check
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o?Running layout versus schematic (LVS) checks?
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o?Understanding and debugging LVS check reports?
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o?Setting up LVS run parameters?
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o?Displaying errors using the graphical user interface?
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o Locating LVS errors
Unit 3
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o Running layout versus schematic checks (continued)?
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o?Debugging LVS with multiple errors?
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o?Using the main debugging tools?
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o?Mismatched nets and mismatched devices?
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o?Shorts locator and opens locator?
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o?Malformed devices?
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o?Pins, parameters, and rewire tools
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o?Unguided debugger lab module?
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o?Running an electrical rules check (ERC)
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