第一階段
部分 1
1 Introduction to the Virtuoso Analog Design Environment
2 Schematic Entry
3 Analog Simulation
4 Displaying Simulation Results
5,
關(guān)于版圖一些基本知識；
部分 2 :?Virtuoso Custom Design Platform 6.14
l?????????IC61 Virtuoso Schematic Editor L/XL presentation, Lei Song;
?????????????????? ? -new features introduction
l?????????IC61 Analog Design Environment L/XL presentation, Lei Song;
?????????????????????-new features introduction
l?????????IC61 Virtuoso Layout Suite L/XL/GXL?presentation,?Amy Zhang;
???????????????????? -new features introduction
???????????????????? -Live demo of?IC61 Virtuoso Layout Suite?L/XL/GXL,Amy Zhang;
l?????????Workshop of Virtuoso Layout Suite XL?.
?
部分 3 :?Virtuoso MMSIM10.1 Overview
l?????????MMSIM10.1 Presentation, Lei Song;
??????????????????-new features introduction
l?????????Workshop of Virtuoso?MMSIM10.1.
部分 4
5 Analyzing Simulation Results
6 Parametric Analysis
7 Using the OCEAN and SKILL Languages
8 Corners Analysis
部分 5
9 Monte Carlo Analysis
10 Component Description Format(CDF)
11 Macromodels, Subcircuits, andInline Subcircuits
12 Hierarchy Editor
13 Inherited Connections
? ??Layout generation
?
??Editing?Virtuoso XL placement
?
??Creating interconnect in Virtuoso?XL
??Using the Wire?Editor
?
??Analyzing and updating data
?
??Working with hierarchical designs and variables
??Generating?abstracts
??Floor planning with Virtuoso?Preview
??Virtuoso Custom Placer setup
??Pin placement with Virtuoso Custom Placer
??Placement?planning and the auto placer
?第二階段
1,
后端設(shè)計關(guān)于DRC檢測和LVS驗證的整個流程；
2,
GDS文件和TF庫文件的導(dǎo)入；
3,
關(guān)于Cadence Virtuoso庫文件的配置；
4,DRC檢測的規(guī)則；
5,版圖設(shè)計中的一些寄生效應(yīng)及其消除方法；
6,其他高級布線的技巧與經(jīng)驗總結(jié)。 |
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